The present invention relates to memory devices and, more particularly, to a system and a method for reducing stress on memory devices.
FIG. 1 shows a conventional system 100 including a memory 102 for storing code and data, and a processor 104 connected to the memory 102 for executing the code stored in the memory 102, and reading data from or writing data to the memory 102. For example, the system 100 can be a system-on-chip (SoC) that is an integrated circuit integrating the processor, memory and other components onto a single chip.
FIG. 2 shows a conventional structure of the memory 102 in the system of FIG. 1. The memory 102 can be a non-volatile memory (NVM), which is widely used to store the code and data. Typically, the NVM is logically divided into many logical memory blocks of equal size, with some of the memory blocks being configured to store the code and some the data. For example, as shown in FIG. 2, the NVM 102 with a size of 1280 kB is divided into first through fifth memory blocks 106-114, each having a size of 256 kB. The first and second memory blocks 106 and 108 store the code, namely code blocks, and the third through fifth blocks 110-114 store the data, namely data blocks. The code in the code blocks 106 and 108 is usually programmed during manufacturing, and seldom reprogrammed by customers. The data blocks 110-114 are read from and written to frequently during operation of the system 100. Writing data to the data blocks includes erasing data previously stored in the data blocks and storing new data in the data blocks. Therefore, the data blocks 110-114 suffer more erasing stress than the code blocks 106-108, and reach erase cycles earlier than the code blocks 106-108. The life length of the system 100 partially depends on the life length of the memory 102, and the life length of the memory 102 is limited by the first memory block of the NVM that reaches the maximum number of erase cycles. It is therefore desirable to find a method for reducing the erase stress on the memory device to extend the life of the SoC.